$9 for SLogic Lite8, $14.9 for SLogic Combo8(LA+4UART+CKLink+DAPLink)

SLogic Lite8 (Logic Analyzer)

channel: 8CH (MAX)
samplerate: 160Msps (MAX)
bandwidth: 320Mb/s (MAX)

supported configuration for continuously sampling

• 160M@2CH
• 80M@4CH
• 40M@8CH

input signal level: 0～3.6V (TTL)

Nice to see a patch for this analyzer, have just received mine (early order) and finally found time to test it.
Tested it including your 0bdfe4ceb03c74fe03c07ba620210ddd00fde4fe commit on your hardware-sipeed-slogic-support branch

Hope to soon see it mainlined into libsigrok.

Currently still running into some issues:

• starting an acquisition sometimes completely freezes libsigrok
• needs to run as root. Fixed on my branch on commit 24978df3a369380466fcb20ced79fae074909e55
• missing dependency on libusb. Fixed on my branch on commit dc604b7fcabec9ff158bb0de1dec7a7bdc76a7ff
• when switching to a sample rate of 64 or 80 MS/s, the number of channels gets correctly reduced to 4, the same when switching to 128 or 160 MS/s it gets reduced to 2. Switching back to 64 or 80 MS/s again gets back to 4 channels. Switching to 40 MS/s or lower won't give back all 8 channels. The device needs to get opened again. Fixed on my branch on commit fe587691af2f86089385a0b145cb2bf2f2e30f5e

Thanks for your work and i'm looking forward to test this device some more !

Very interesting driver for this new very little logic analyzer (and more...)
Would be nice to also add the udev rules, update [contrib/60-libsigrok.rules]

@@ -312,6 +312,9 @@ ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea60", ENV{ID_SIGROK}="1"
# UNI-T UT-D09 multimeter cable (for various UNI-T and rebranded DMMs)
ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea80", ENV{ID_SIGROK}="1"

+# Sipeed SLogic Combo 8
+ATTRS{idVendor}=="359f", ATTRS{idProduct}=="0300", ENV{ID_SIGROK}="1"
+
# Sysclk LWLA1016
ATTRS{idVendor}=="2961", ATTRS{idProduct}=="6688", ENV{ID_SIGROK}="1"

Very interesting driver for this new very little logic analyzer (and more...) Would be nice to also add the udev rules, update [contrib/60-libsigrok.rules]

@@ -312,6 +312,9 @@ ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea60", ENV{ID_SIGROK}="1" # UNI-T UT-D09 multimeter cable (for various UNI-T and rebranded DMMs) ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea80", ENV{ID_SIGROK}="1" +# Sipeed SLogic Combo 8 +ATTRS{idVendor}=="359f", ATTRS{idProduct}=="0300", ENV{ID_SIGROK}="1" + # Sysclk LWLA1016 ATTRS{idVendor}=="2961", ATTRS{idProduct}=="6688", ENV{ID_SIGROK}="1"

Yes, i already fixed that on my branch: master...MartinHerren:libsigrok:slogiclite8
Changes

• Added udev rules
• Fixed channel number selection to get again 8 channels when selecting 40 MS/s or less
• Fixed build dependencies

I don't know if @taorye is still around and wants to update his PR or if we should open a new one.

There are still issues that the it regularly freezes and needs unplugging/replugging.

Very interesting driver for this new very little logic analyzer (and more...) Would be nice to also add the udev rules, update [contrib/60-libsigrok.rules]
@@ -312,6 +312,9 @@ ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea60", ENV{ID_SIGROK}="1" # UNI-T UT-D09 multimeter cable (for various UNI-T and rebranded DMMs) ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea80", ENV{ID_SIGROK}="1" +# Sipeed SLogic Combo 8 +ATTRS{idVendor}=="359f", ATTRS{idProduct}=="0300", ENV{ID_SIGROK}="1" + # Sysclk LWLA1016 ATTRS{idVendor}=="2961", ATTRS{idProduct}=="6688", ENV{ID_SIGROK}="1"

Yes, i already fixed that on my branch: master...MartinHerren:libsigrok:slogiclite8 Changes

* Added udev rules

* Fixed channel number selection to get again 8 channels when selecting 40 MS/s or less

* Fixed build dependencies

I don't know if @taorye is still around and wants to update his PR or if we should open a new one.

There are still issues that the it regularly freezes and needs unplugging/replugging.

Indeed there are a few issue[S] (I try to have it working under Linux) and it's rather strange behaviour in most of my tests, I do not have much time to investigate fully at the moment.

Regarding the PR, I do not know @taorye, and I am rather new to using GIT, was stuck to Subversion for some reasons :) so I do not know the best way to proceed, neither the relation between @taorye and Sipeed. There is an email address on her/his github page though.

I hope to free some time later this month to investigate more, let's see if this dream becomes some sort of reality

Hej,

we'll see. If i have time to fix the usb issue and the original author didn't react, i'll probably open a new PR.

Thanks for your attention

Very interesting driver for this new very little logic analyzer (and more...) Would be nice to also add the udev rules, update [contrib/60-libsigrok.rules]
@@ -312,6 +312,9 @@ ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea60", ENV{ID_SIGROK}="1" # UNI-T UT-D09 multimeter cable (for various UNI-T and rebranded DMMs) ATTRS{idVendor}=="10c4", ATTRS{idProduct}=="ea80", ENV{ID_SIGROK}="1" +# Sipeed SLogic Combo 8 +ATTRS{idVendor}=="359f", ATTRS{idProduct}=="0300", ENV{ID_SIGROK}="1" + # Sysclk LWLA1016 ATTRS{idVendor}=="2961", ATTRS{idProduct}=="6688", ENV{ID_SIGROK}="1"

Yes, i already fixed that on my branch: master...MartinHerren:libsigrok:slogiclite8 Changes

* Added udev rules

* Fixed channel number selection to get again 8 channels when selecting 40 MS/s or less

* Fixed build dependencies

I don't know if @taorye is still around and wants to update his PR or if we should open a new one.

There are still issues that the it regularly freezes and needs unplugging/replugging.

I'll come back soon. There are more to be updated before next year.

Hello, guys.

I have attempted to patch the mainline of libsigrok with MartinHerren's branch, specifically the slogiclite8 branch. I have tested it with the PulseView mainline.

I have encountered an issue where setting the sampling frequency to 5MHz or below can cause data acquisition to freeze. This issue is 100% reproducible.

In the case of a sampling rate greater than 5MHz, it works fine without any issues (?

my device is the Sipeed Slogic Combo 8.

So is it dead?

So is it dead?

Certainly looks like it to me. There hasn't been a firmware release since 2023-09 for the SLogic Combo 8, and the provided PulseView AppImage hasn't been updated since 2023-08.. and I don't think there's another PR.

Looks a lot like vaporware tbh.. Hopefully development picks up again at some point. I don't understand why it wasn't at least made open source if there's not enough resources to work on it. :/

Hm, I just noticed it actually uses the M0S module inside, apparently!

Hej all,

Sorry for the late reply, didn't have time to use my Sipeed SLogic recently.

Juste rebased and rebuilt by branch (with @taorye's original support plus my fixes) on latest libsigrock's master branche.

Will try to use it during next week to try to reproduce @yjun123's issue and also my USB freezes.

I don't think it is a 'dead project' as they are still selling it. They haven't published new firmware and software as they might consider it works 'good enough' for them. Hopefully a stable version will end up officially in libsigrock.

I'm not even sure github is the correct place to open a PR for libsigrock as they never reacted to this PR. It is a read-only mirror but they say 'PR welcome'. For the moment i'll try to keep my branch alive and up to date with upstream to be able to continue to use my own device.

If it works stable enough and other people including upstream are interested i can open a new pull request.

My branch: https://github.com/MartinHerren/libsigrok/tree/slogiclite8, rebased on today's upstream:master.

@MartinHerren since this PR is close due to @taorye deleting the branch, are you planning to open a new PR from your branch?

Sipeed provides an AppImage binary version of Pulseview with a libsigrok modified to support this hardware, without releasing the source code. Isn't that a violation of the GPL?

A request was made here sipeed/sipeed_wiki#698, I've actually just emailed support to request the source code.

@0xDRRB, @g5pw : after this request, email and this post, @sipeed has opensourced his repository here.
Haven't compared the repo and this PR but I'm not sure there is more information to obtain...

Confusingly, there are two branches in sipeed/sigrok_slogic with very different implementations. Can anyone tell from the code which one would be better suited for merging into the mainline?

EDIT: branch hardware-sipeed-slogic-support doesn't build, so I guess hardware-sipeed-slogic-analyzer-support then?

Seems like the repo is still getting updates

The process of integrating the latest developments into the main branch has officially commenced. Community members and contributors are invited to monitor the progress through the dedicated Pull Request sigrokproject/libsigrok#262. This PR serves as a pivotal point for tracking updates, facilitating discussions, and ensuring transparency in the development cycle.

Oh, great news ! Thanks !

Sorry didn't have any time for follow up recently, still have my SLogic 8 and ready to try it again !